VLSI
Module 1: Introduction to VLSI
- volution of VLSI Systems
- Applications of VLSI Systems
- Processor Based Systems
- Embedded Systems
- FPGA Based Systems
- Digital System Design Using FPGAs
- Spartan-3 FPGAs
- Introduction to VHDL language
Module 2: Digital Electronics
- Introduction to Digital Electronics
- Number systems
- Code conversions
- Arithmetic’s
- Boolean algebra
- Logic gates
Module 3: Combinational logic design
- Standard representation of logical functions
- Karnaugh map method
- MSI circuits
- Multiplexers/demultiplexers
- Adders / subtractors
- Arithmetic Logic Unit (ALU)
- Encoders/ Decoders
Module 4: Flip Flops
- Flip-flops
- Type of Flip flops
- Conversion of flip flops
- Application of flip flops
Module 5: Sequentional circuit design
- Registers
- Types of shift registers
- Application of registers
- Counters
- Ripple or Asynchronous counters
- Synchronous counters
- Clocked sequential circuits
Module 6: Designing of Memories
- Introduction
- Memory Organization and operation
- Expanding memory size
- Expanding memory capacity
- Different types of memories
Module 7: Programmable Logic devices
- Introduction
- Programmable logic array (PLAs)
- Programmable array logic (PALs)
- Complex programmable logic devices (CPLDs)
- Field programmable gate array (FPGA)
- Computer-Aided Design Tools (CAD)
Module 8: Circuit Design with VHDL
- Introduction to VHDL
- Code structure
- Library Functions
- Entity
- Architecture
- Configuration Declaration
- Package Declaration
Module 9: Elements of VHDL LANGUAGES
- Different Data types
- Operators
- Attributes
- Generic
- Ident
Module 10: ifiers
- Variables & Signals
Module 11: Different types of VHDL Modeling
- Behavioral modeling
- Modeling techniques
- If statement
- Case statement
- Wait statement
- Loop statement
- Process statement
Module 12: Dataflow modeling
- When statements.
- Block statement
- Generate statement
Module 13: Structural Modeling
- Component declaration
- Component instantiation
Module 14: Test Bench
- Modeling a Test Bench
- Test Bench for Combinational Circuits
- Test Bench for Sequential Circuits
Module 15: Design and synthesis by using Verilog HDL
Module 16: Introduction to Verilog HDL
- Evolution of CAD
- Typical Design flow
- Importance of HDL’s
- Popularity of Verilog HDL
Module 17: Modeling Concepts
- Design methodologies
- Module concept
- types of modeling
Module 18: Basic Concepts
- Lexical Conventions
- Number Specifications
- Strings
- Data Types
- System Task
- Compiler Directives
Module 19: Modules
- Continous Assignments
- Delays
- Expression Operators
- Operators Types
Module 20: Behavioural Modeling
Module 21: Structured Procedures
Module 22: Intial Statement
Module 23: Always Statement
Module 24: Event- Base Timing Control
Module 25: Conditional Statements
Module 26: If Statements
Module 27: Case Statements
Module 28: Loop Statements
Module 29: Task and Functions
- Different between Task and Function
- Function
- Task
Module 30: Switch Level Modeling